1. Field of the Invention
The present invention relates to the field of dynamic logic design and, more particularly, to a dynamic pulse register.
2. Description of the Related Art
Many circuit designs employ dynamic logic. Unlike static logic gates, which only transition upon a corresponding input transition, dynamic logic gates may transition both during a precharge phase and an evaluate phase of a clock signal. In the precharge phase, a dynamic node is conditionally charged to a given logic state. In the evaluate phase, the node either remains charged or is discharged in accordance with the particular logic function being implemented. Correct operation of a dynamic logic gate thus depends upon the capacitance of the dynamic node retaining the precharged value until the precharge phase begins. Dynamic logic, while more complex than static logic, may be advantageously employed to achieve higher operating speeds.
One type of dynamic logic design technique is self-resetting circuitry. Instead of using the clock to control when the precharge and evaluate phases occur, narrow pulse signals are employed to initiate precharge and evaluation. Accordingly, pulse input data is often required as input to a logic block implemented in self-resetting circuitry.
As used herein, a "pulse" is a signal including two transitions: an inactive-to-active transition followed by an active-to-inactive transition. For circuits in which a logic high state represents the active state, a pulse includes a transition from a logic low state to a logic high state, followed by a transition from the logic high state to the logic low state. The amount of time a pulse remains in the active state is known as the pulse width. Self-resetting circuits may be configured to generate adjustable pulse output widths.
Turning now to FIG. 1A, a pulse circuit 10 is depicted which generates pulse output data from a given input. As shown, pulse circuit 10 includes a register 14 and a pulse generation circuit 18. Register 14 receives input data 12 and a standard clock 16, while pulse generation circuit 18 receives the contents of register 14 and conveys pulse data 20 as output.
Register 14 receives input data 12 when standard clock 16 becomes active. This information is then conveyed to pulse generation circuit 18. Because the pulse width of the standard clock signal may be different from the desired pulse width for pulse data 20, pulse generation circuit 18 conveys pulse data 20, which is of the desired pulse width. A disadvantage of pulse circuit 10, however, is that the input data must propagate through two stages of logic to reach the output, thus increasing delay.
Turning now to FIG. 1B, another technique for pulse generation is exemplified by pulse circuit 30. As depicted, pulse circuit 30 includes a register 22 and a pulse clock circuit 24. Register 22 receives input data 12, a pulse clock 26, and conveys pulse data 20 as output. Pulse clock circuit 24 receives standard clock 16 and conveys pulse clock 26 as output.
Pulse circuit 30 employs pulse clock circuit 24 to generate pulse clock 26, which has a pulse width which is desired for pulse data 20. In this manner, pulse clock 26 may be used to read from register 22, thereby conveying pulse data 20 with a pulse width equal to that of pulse clock 26. Like pulse circuit 10, however, two stages of logic are employed in generating pulse data 20 from input data 12 in pulse circuit 30. The overall delay is similarly increased.
Turning now to FIG. 1C, another pulse generation circuit, pulse circuit 40, is shown. As depicted, pulse circuit 40 includes a register 32 and a custom clock header 36. Register 32 receives input data 12, a special pulse clock 38, and conveys pulse data 20 as output. Custom clock header 36 receives early clock 34 as input and conveys special pulse clock 38 as output.
An early clock signal such as early clock 34 may be used as an input to custom clock header 36. The resulting output of custom clock header 36, special pulse clock 38, is a clock signal of the desired pulse width which aligns precisely with the rising edge of a standard clock signal. Because the rising edge of early clock 34 precedes a corresponding rising edge of a standard clock signal, special pulse clock 38 is available to register 32 at the same time the input data is sampled, thus reducing delay.
Early clock signals are not available in all logic circuits, however. Even if an early clock signal is available, design of custom clock header 36 may be difficult, since a precision early clock-to-standard clock delay match circuit is required. Precise rise and fall slew rates requirements for special pulse clock 38 add further design difficulties.
It would therefore be desirable to have a dynamic pulse register which employs a standard clock signal and exhibits reduced propagation delay.